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PhoxTrot

PhoxTrot

Photonics For High-Performance, Low-Cost & Low-Energy Data Centers, High Performance Computing Systems: Terabit/S Optical Interconnect Technologies For On-Board, Board-To-Board, Rack-To-Rack Data Links

PhoxTrot is a large-scale research effort focusing on high-performance, low-energy and cost and small-size optical interconnects across the different hierarchy levels in Data Center and High-Performance Computing Systems: on-board, board-to-board and rack-to-rack. PhoxTrot will tackle optical interconnects in a holistic way, synergizing the different fabrication platforms (CMOS electronics, Si-photonics, polymers, glass, III-Vs, plasmonics) in order to deploy the optimal "mix&match" technology and tailor this to each interconnect layer. PhoxTrot follows a layered approach from near-term exploitable to more forward looking but of high expected gain activities. The main objectives of PhoxTrot include the deployment of:

  1. generic building block technologies (transmitters, modulators, receivers, switches, optochips, multi- and single-mode optical PCBs, chip- and board-to-board connectors) that can be used for a broad range of applications, extending performance beyond Tb/s and reducing energy by more than 50%.
  2. a unified integration/packaging methodology as a cost/energy-reduction factor for board-adaptable 3D SiP transceiver and router optochip fabrication.
  3. the whole "food-chain" of low-cost and low-energy interconnect technologies concluding to 3 fully functional prototype systems: an >1Tb/s throughput optical PCB and >50% reduced energy requirements, a high-end >2Tb/s throughput optical backplane for board-to-board interconnection, and a 1.28Tb/s 16QAM Active OpticalCable that reduces power requirements by >70%.
PhoxTrot

CTI within PhoxTrot focuses on:

  • Architectures for the different hierarchy layers, relying on optical interconnection module specifications. Data Center and HPC architectures are also studied from a holistic perspective, addressing the interaction between the different architectural layers. Candidate topologies and architectures are evaluated theoretically considering scalability issues and packaging constraints.
  • Studies on traffic profiles for HPC and Data Centers, in order to identify appropriate applications and traffic patterns. These will be used for the definition of realistic application workload models.
  • Evaluation of performance of the proposed architectures through simulations, using realistic HPC and DC application workload models.
  • Optical packet router architectures for HPC and DataCenters supporting Advanced Modulation

Πρόσθετες Πληροφορίες

  • Έναρξη: 10ος/2012
  • Λήξη: 9ος/2016
  • Χρηματοδότηση: European Commission, FP7-ICT-2011-8, Project Grant agreement no. 318240
  • Συνεργάτες: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V, VERTILAS GMBH, XYRATEX TECHNOLOGY LIMITED, AMS AG, MEADVILLE ASPOCOMP INTERNATIONAL LIMITED, GESELLSCHAFT FUR ANGEWANDTE MIKRO UND OPTOELEKTRONIK MIT BESCHRANKTERHAFTUNG AMO GMBH, INSTITUTE OF COMMUNICATION AND COMPUTER SYSTEMS, DAS PHOTONICS SL, PHOENIX BV, CENTRE FOR RESEARCH AND TECHNOLOGY HELLAS, COMPAS ELECTRO-OPTICAL SYSTEMS LTD, BRIGHT PHOTONICS BV, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, KARLSRUHER INSTITUT FUER TECHNOLOGIE, SYDDANSK UNIVERSITET, UNIVERSITAT POLITECNICA DE VALENCIA, INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW, TYCO ELECTRONICS NEDERLAND BV
  • Διάρκεια (μήνες): 48

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